This invention relates generally to semiconductor packaging, and specifically to a board-on-chip package that includes a semiconductor die, and a substrate bonded circuit side down to the die. This invention also relates to a method for fabricating the package, and to electronic assemblies incorporating the package.
One type of semiconductor package is referred to as a xe2x80x9cchip scale packagexe2x80x9d. Chip scale packages are also referred to as xe2x80x9cchip size packagesxe2x80x9d, and the dice are referred to as being xe2x80x9cminimally packagedxe2x80x9d. Chip scale packages can be fabricated in xe2x80x9cuncasedxe2x80x9d or xe2x80x9ccasedxe2x80x9d configurations. Uncased chip scale packages have a xe2x80x9cfootprintxe2x80x9d (peripheral outline) that is about the same as an unpackaged die. Cased chip scale packages have a peripheral outline that is slightly larger that an unpackaged die. For example, a footprint for a typical cased chip scale package can be about 1.2 times the size of the die contained within the package.
A conventional chip scale package includes a substrate bonded to the die. Typically, the substrate comprises an organic material, such as bismaleimide triazine (BT), an epoxy resin (e.g., xe2x80x9cFR-4xe2x80x9d) or a polyimide resin. The substrate includes a pattern of conductors, such as copper traces, that are wire bonded, or other wise electrically connected, to bond pads, or other connection points, on the die.
The substrate also includes external contacts in electrical communication with the conductors. Typically, the external contacts comprise solder balls arranged in a dense array, such as a ball grid array (BGA), or a fine ball grid array (FBGA). These dense arrays permit a high input/output capability for the chip scale package. For example, a FBGA on a chip scale package can include several hundred solder balls. The pattern of conductors on the substrate, and the associated bonding sites for the external contacts, is sometimes referred to as a xe2x80x9ccircuitxe2x80x9d.
One type of chip scale package is known as a board-on-chip (BOC) package. With a BOC package the substrate (i.e., the board) is bonded to the circuit side (face) of the die, and wire bonds are made between the conductors on the substrate and the bond pads on the die.
Referring to FIGS. 1A and 1B, a conventional BOC package 10 is illustrated. The BOC package 10 includes a semiconductor die 12 having a circuit side 14, and a pattern of bond pads 16 on the circuit side 14. The bond pads 16 are in electrical communication with the integrated circuits and semiconductor devices contained on the die 12. The BOC package 10 also includes a substrate 18 bonded to the circuit side 14 of the die 12. The substrate 18 has a circuit side 22 containing a pattern of conductors 24, and an adhesive layer 20, which bonds the substrate 18 to the die 12. The substrate 18 has a peripheral outline that is smaller than the peripheral outline of the die 12, such that the bond pads 16 are not covered by the substrate 18 and the adhesive layer 20.
The BOC package 10 also includes an array of external contacts 26 on the substrate 18 in electrical communication with the conductors 24. The external contacts 26 comprise solder balls in a grid array, such as a ball grid array (BGA) or a fine ball grid array (FBGA). The external contacts 26 are bonded to ball bonding sites 30 on the conductors 24 using a bonding technique such as soldering, welding or brazing. A solder mask 32 on the substrate 18 facilitates bonding and electrical isolation of the external contacts 26. The conductors 24 also include wire bonding sites 30, and wires 34 are wire bonded to the wire bonding sites 30, and to the bond pads 16 on the die 12. The BOC package 10 also includes an encapsulant 36 that encapsulates the wires 34 and the associated wire bonds on the wire bonding sites 30 and on the bond pads 16. Typically, the encapsulant 36 comprises a Novolac based epoxy formed in a desired shape using a transfer molding process, and then cured using an oven.
One feature of this type of BOC package 10 is that using standard wire bonding techniques the wires 34 are formed with a loop height W1. In addition, the encapsulant 36 must have a width X1, and a thickness Y1 which insures that the wires 34 are fully covered by a desired covering thickness Z1 (e.g., 0.02 mm to 0.10 mm). Accordingly, the thickness Y1 of the encapsulant 36 must be selected to be at least equal to the loop height W1 plus the covering thickness Z1 (Y1=W1+Z1). An overall height YP (profile) of the package 10 is thus affected by the loop height W1, by the covering thickness Z1, and by the thickness Y1 of the encapsulant 36.
It would be advantageous to be able to decrease the loop height W1 and the thickness Y1 of the encapsulant 36. In particular, reductions in the loop height W1 and the thickness Y1 of the encapsulant 36 would allow the overall height YP of the package 10 to be decreased. Similarly, it would be advantageous to be able to decrease the width X1 of the encapsulant 36, as this would decrease the footprint of the BOC package 10.
Another feature of the BOC package 10 is that the relatively large thickness Y1 of the encapsulant 36 forms a recess 38 proximate to the external contacts 26. In order to make electrical contact with a mating substrate, such as a printed circuit board, the external contacts 26 must have a diameter D1 that is larger than the depth D2 of the recess 38. In order to satisfy this requirement the external contacts 26 must be larger than otherwise required. It would be advantageous to be able to decrease the depth D2 of the recess 38.
Yet another feature of the BOC package 10 is that during molding of the encapsulant 36, some mold material may bleed onto the solder mask 32. The mold bleed can adversely affect bonding of the external contacts 26 to the bonding sites 28. The mold bleed can also adversely affect the electrical connections to the external contacts 26, and the cosmetic appearance of the BOC package 10.
The present invention is directed to an improved BOC package that has a reduced thickness, and a smaller footprint than the prior art BOC package 10. In addition, the BOC package uses less encapsulant material, has less mold bleed, and a substantially planar encapsulant surface. The present invention is also directed to a method for fabricating the improved package, and to improved electronic assemblies incorporating the package.
In accordance with the present invention, an improved BOC package, a method for fabricating the BOC package, and electronic assemblies incorporating the BOC package are provided.
The BOC package includes a semiconductor die, a substrate adhesively bonded to the die, and an array of external contacts (e.g., BGA solder balls) on the substrate. The BOC package also includes wires that are wire bonded to the die and to the substrate, and molded segments on either side of the substrate for encapsulating the wires.
The semiconductor die includes a circuit side (face) having a pattern of die contacts in electrical communication with the integrated circuits contained on the die. The substrate also includes a circuit side (face) having a pattern of conductors and wire bonding sites located outside of the peripheral edges of the substrate. In addition, the substrate includes a back side with the external contacts and ball bonding sites for bonding the external contacts to the substrate.
In the BOC package the substrate is bonded to the die with its circuit side xe2x80x9cdownxe2x80x9d, or xe2x80x9cfacingxe2x80x9d the circuit side of the die (i.e., circuit side to circuit side). Stated differently, the circuit side of the substrate faces xe2x80x9cinxe2x80x9d relative to the exterior of the package, rather than xe2x80x9coutxe2x80x9d as with conventional BOC packages. This arrangement permits a loop height of the wires, and a height of the molded segments, to be decreased by a distance equal to a thickness of the substrate. In addition, a width of the molded segments is decreased, such that a footprint of the BOC package is decreased. Further, a planarity of exterior surfaces of the molded segments is improved, and mold bleed during formation of the molded segments is decreased.
The method for fabricating the package includes the steps of: providing the semiconductor die with the circuit side having the die contacts; providing the substrate with the circuit side having the pattern of conductors and wire bonding sites, and with the back side having the ball bonding sites in electrical communication with the conductors; adhesively bonding the circuit side of the substrate to the circuit side of the die; wire bonding the wires to the wire bonding sites on the substrate and to the die contacts on the die; forming the molded segments to encapsulate the wires; and bonding the external contacts to the ball bonding sites on the substrate.
An electronic assembly, such as a multi chip module, includes a substrate and multiple BOC packages flip chip mounted the substrate. Because the BOC packages have a reduced height, a height of the assembly is also reduced.